View HV7321K6-G_8675878.PDF datasheet online --- IC-ON-LINE

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? 2016 microchip technology inc. ds20005639a-page 1 hv7321 features ? power sequencing free 5 output levels including rtz (return-to-zero) ? -44 db single-cycle pulse-inversion second harmonic distortion (hd2) at 5 mhz ? output voltage up to 80v ? 2.5a peak output current ? 300 ma current from v pp1 /v nn1 in cw mode-0 ? integrated t/r switch & rx damper switch ? bleeder switches achieve true zero during rtz ? supports both transparent and re-timing mode ? re-timing clock frequency supports up to 220 mhz ? built-in output protection diodes and clamp diodes ? +2.5/+3.3v input logic ? built-in cw switches to pair with external cw transmitters (cw mode-1) ? 9 mm x 9 mm 64-lead vqfn package applications ? medical ultrasound imaging systems ? ndt ultrasound ? piezoelectric or capacitive transducer drivers general description the hv7321 is a 4-channel, 5-level, ultrasound transmitter with built-in t/r switches, output protection diodes and clamp diodes. the hv7321 can provide up to 2.5a and the output voltage swing can be up to 80v. the hv7321 supports both transparent and re-timing mode. the re-t iming clock frequency can support up to 220 mhz. the re-timing feature helps reduce the output jitter in troduced by the driving the field-programmable gate array (fpga). the hv7321 has two different modes for cw transmission, cw-mode 0 and cw-mode 1. in cw-mode 0 (mode = 0, pws = 0), the v pp1 and v nn1 rails are used for cw transmission. the output current is reduced in cw mode-0. in cw-mode 1, the hv7321 accepts the output of an external cw beamformer as cw source. the hv7321 is lvcmos 2.5v/3.3v input compatible, which can be interfaced with the fpga directly. the hv7321 is available in a 9 mm x 9 mm 64-lead vqfn package. 4-ch. 5-level 80v high-voltage ultrasound pulser with t/r switches
hv7321 ds20005639a-page 2 ? 2016 microchip technology inc. package types 65 v sub 63 64 60 61 59 58 54 55 56 57 62 50 51 52 53 49 pos0 neg0 sel0 mode v dd gnd v gn v pp0 v pp0 c pf0 c nf0 v nn0 v nn0 v nn2 v nn1 c nf1 15 16 12 13 11 10 6 7 8 9 14 2 3 4 5 1 cw in0 sel1 neg1 pos1 pws clk gnd v ll ren neg2 cw in2 sel3 pos2 20 19 22 21 25 24 26 27 31 30 29 28 23 32 18 17 cw in1 oen sel2 neg3 pos3 cw in3 otp n v dd gnd v gp v pp0 c pf0 v nn0 v nn2 v nn1 c nf1 v pp0 c nf0 v nn0 36 35 38 37 41 40 42 43 47 46 45 44 39 48 34 33 c pf1 v pp1 tx0 rx0 r gnd rx1 c neg r gnd tx3 c pf1 v pp1 rx3 rx2 tx2 c pos tx1
? 2016 microchip technology inc. ds20005639a-page 3 hv7321 hv7321 ? block diagram rb oen pos3 neg3 sel3 clk x0 rx0 +2.5v/3v +5v -10v gnd v gn v sub c neg v nn2 c nf0 v nn0 c nf1 v nn1 tx0 rx0 r gnd tx1,2,3 v ll v dd c pos v gp c pf0 v pp0 c pf1 v pp1 2 f 2 f v pf1 v gn v pp1 v pp0 v neg gnd v gn v nf1 v nn2 v pp0 sub v pos to ch. 1-3 0 to +80v 0 to +80v 0 to -80v 0 to -80v 2 f 1 f 2 f 2 f 2 f 2 f 2 f 100v 100v v gn v pf0 gnd 1 f 1 f 100v 2 f 1 f 100v 2 f 2 f 100v v nf0 v gp v nn0 v gp v nn1 v pp1 to cwsw1-3 cwsw0 v pf0 v nf0 v pf0 v neg v nf1 v pos v nn0 v nn1 rtzsw0 trsw0 rb rxdmp0 r gnd 1 of 4 channels +10v lr v pos lr v pf0 lr v pf1 rx1,2,3 lr v neg lr v nf0 lr v nf1 sel0 neg0 pos0 otp n pws ren mode cw in0-3 logic and retiming
hv7321 ds20005639a-page 4 ? 2016 microchip technology inc. hv7321 ? typical application circuit x0 +80v v pf1 v nn1 tx0 -60v v pp0 v nn0 -80v +60v 1 of 4 channels v dd cw in3 gnd +2.5v v ll pws pos3 v sub mode ren tx1-3 rx1-3 rx0 r gnd rtzsw cwsw rxdmp trsw v gp -10v oen to other ics ctrn[3:0] otp n dt[63:0] c ll = 2 f 10v c dd = 2f 10v c gp = 2 f 16v c pp0 = 2 f 100v c pp1 = 2 f 100v c nn1 = 2 f 100v c gn = 2 f 16v connect to a low-voltage cw source (such as the md1730) c cpos = 1f 10v c pos c pf0 c pf1 c cpf1 = 2 f 10v c nf0 c cneg = 1 f 10v c neg c nf1 c cnf1 = 2 f 10v c nn0 = 2 f 100v c cnf0 = 2 f 10v c cpf1 = 2 f 10v v nn2 v nf1 txfpga i/os +5v +10v v pp1 rx0 v gn r gnd sub trsw decode & level shift v pf0 v nf0 cw in2 cw in1 cw in0 clk neg3 sel3 pos0 neg0 sel0 otp n for cw mode-1
? 2016 microchip technology inc. ds20005639a-page 5 hv7321 1.0 electrical characteristics absolute maximum ratings ? positive logic supply (v ll ).......................................................................................................................... -0.5 v to +5.5v all i/o & clk pin voltage (v io )................................................................................................................... -0.5v to +5 .5v positive voltage supply (v dd )..................................................................................................................... -0.5v to +5.5v positive gate driver supply (v gp ) ............................................................................................................. -0.5v to +13.5v negative gate driver supply (v gn ) ........................................................................................................... -13.5v to +0.5v high voltage positive supply (v pp0,1 ) .......................................................................................................... -1.0v to +85v high voltage negative supply (v nn0,1,2 )...................................................................................................... -85v to +1.0v cw input voltage (v cwin ) .......................................................................................................................... -7.5 v to +7.5v tx pin voltage (v tx ).............................................................................................................................. ....... -85v to +85v rx pin to gnd voltage (v rx ) ....................................................................................................................... 0.7 to 1.4v operating temperature ......................................................................................................... ....................... 0c to +85c storage temperature ............................................................................................................ ................... -55c to +150c maximum junction temperature...... ............................................................................................. ......................... +130c maximum not-latch-up current ................................................................................................... ........................ +100 ma esd rating cw in ,tx, v pp , v nn pins ......................................................................................................................500 v esd rating ? all other pins ......... ........................................................................................... ................................... 2kv ? notice: stresses above those listed under ?maximum ratings? ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at th ose or any other conditions above those indicated in the operational sections of this specificat ion is not intended. exposure to maximum rating conditions for extended periods may affect device reliability. electrical characteristics electrical specifications: v ll = +2.5v, v dd = +5.0v, v pp0,1 = +80v, v nn0,1,2 = -80v, v gp = +10v, v gn = -10v, v sub = 0v, pws = oen = ren = 1, t a = 25c, unless otherwise s pecified. parameters in bold apply over the operating temperature range of t a = t j = 0 to +85c. parameter sym. min. typ. max. unit conditions operating supply voltages positive logic supply v ll 2.25 2.50 3.60 v note 1 positive voltage supply v dd 4.75 5.0 5.25 v note 1 positive gate driver supply v gp 8.0 10 12 v note 1 see table 3-1 . negative gate driver supply v gn -12 -10 -8.0 high voltage positive supply v pp0 0 ? 80 v note 1 must be v pp0 v pp1 v pp1 0 ? 80 high voltage negative supply v nn0 -80 ? 0 v note 1 must be v nn0 ? v nn1 v nn1 -80 ? 0 operating supply current v ll quiescent current i llq ?0.060.7 a oen = ren = 0 v dd quiescent current i ddq ?3080a v pp0 quiescent current i pp0q ?0.37 6 a v nn0 quiescent current i nn0q -9 -0.78 ? a v pp1 quiescent current i pp1q ?0.4410 a v nn1 quiescent current i nn1q -10 -1.46 ? a v nn2 quiescent current i nn2q -7 -3.84 ? a note 1: characterized only; not 100% tested in production. 2: design guidance only.
hv7321 ds20005639a-page 6 ? 2016 microchip technology inc. v dd current i dden ?0.91.0ma f = 0 mhz f clk = 0 mhz mode = 0 or 1 v pp0 current i pp0en ? 0.1 0.13 ma v nn0 current i nn0en -0.12 -0.1 ? ma v pp1 current i pp1en ? 0.1 0.13 ma v nn1 current i nn1en -0.12 -0.1 ? ma v nn2 current i nn2en -0.05 -0.03 ? ma v ll current with re-timing i llrt ? 0.11 0.3 ma f clk = 80 mhz tx one-channel output, no load, continuous, note 1 v dd current with re-timing i ddrt ?7.08 8 ma v ll max. current of sel = 0/1 i ll5 ?2340 a clk = 0 pws = 1 mode = 0 i pp05 /i nn05 and i pp15 /i nn15 are calculated using tx one channel output continuous, no load, at 5mhz. v dd max. current of sel = 0/1 i dd5 ?1.51.7ma v gp max. current of sel = 0/1 i gp5 ?2.6 4ma v gn max. current of sel = 0/1 i gn5 -14 -9 ? ma v pp0 current of sel = 0 ( 1 ) i pp05 ? 136 146 ma v nn0 current of sel = 0 ( 1 ) i nn05 -132 -125 ? ma v pp1 current of sel = 1 ( 1 ) i pp15 ? 148 158 ma v nn1 current of sel = 1 ( 1 ) i nn15 -150 -143 ? ma v gp current of sel = 1 i gpcw ? 1.0 2.0 ma tx one-channel output 5 mhz, continuous, no load v pp1 /v nn1 =5v pws = mode = 0 cw mode-0, note 1 v gn current of sel = 1 i gncw -8.0 -5.0 ? ma v pp1 current of sel = 1 i pp1cw ?1726ma v nn1 current of sel = 1 i nn1cw -20 -15 ? ma cwsw high-voltage analog switch cw switch input voltage v cwin0?3 -7.0 ? +7.0 v cwsw analog switch on-resistance ( 1 ) r cwsw ? 26.5 35 ? i cwsw = 100 ma trsw off withstand voltage v cwsw -80 ? +80 v i sw = 1.0 a cwsw off capacitance to gnd c cwsw ?5.0? pf mode = 1, 1 mhz, 0 dbm, dc 0v, note 1 cwsw on capacitance to gnd ? 60 ? cwsw switching on time t cwsw ? 800 1100 ns 50% mode rise to cwsw on/off note 1 cwsw switching off time ? 66 90 tx output p-channel mosfet on v pp0 on-resistance r on_p0 ?8.519 ? i sd = 100 ma peak output current i out_p0 11.5?a v pp0 = +25v, r l = 1.0 ? to gnd note 1 2.0 2.8 ? a v pp0 = +80v, r l = 1.0 ? to gnd note 1 electrical character istics (continued) electrical specifications: v ll = +2.5v, v dd = +5.0v, v pp0,1 = +80v, v nn0,1,2 = -80v, v gp = +10v, v gn = -10v, v sub = 0v, pws = oen = ren = 1, t a = 25c, unless otherwise s pecified. parameters in bold apply over the operating temperature range of t a = t j = 0 to +85c. parameter sym. min. typ. max. unit conditions note 1: characterized only; not 100% tested in production. 2: design guidance only.
? 2016 microchip technology inc. ds20005639a-page 7 hv7321 tx output p-channel mosfet on v pp1 on-resistance at pws = 1 r on_p1 ?1621 ? i sd = 100 ma on-resistance at pws = 0 ? 33 43 peak output current at pws = 1 ( 1 ) i out_p1 0.8 1.0 ? a v pp0,1 = +25v, r l = 1.0 ? to gnd 1.5 1.75 ? v pp0,1 = +80v, r l = 1.0 ? to gnd peak output current at pws = 0 ( 1 ) 0.4 0.5 ? v pp0,1 = +25v, r l = 1.0 ? to gnd 0.8 0.95 ? v pp0,1 = +80v, r l = 1.0 ? to gnd tx output n-channel mosfet on v nn0 on-resistance r on_n0 ?810 ? i sd = 100 ma peak output current ( 1 ) i out_n0 -1.4 -1.7 ? a v nn0 = -25v, r l = 1.0 ? to gnd -2.0 -2.3 ? a v nn0 = -80v, r l = 1.0 ? to gnd tx output n-channel mosfet on v nn1 on-resistance at pws = 1 r on_n1 ?1113 ? i sd = 100 ma on-resistance at pws = 0 ? 36 45 peak output current at pws = 1 ( 1 ) i out_n1 ? -1.2 -1.0 a v nn0,1 = -25v, r l = 1.0 ? to gnd ? -1.6 -1.3 v nn0,1 = -80v, r l = 1.0 ? to gnd peak output current at pws = 0 ( 1 ) ? -0.4 -0.3 v nn0,1 = -25v, r l = 1.0 ? to gnd ? -0.55 -0.4 v nn0,1 = -80v, r l = 1.0 ? to gnd tx damping p-channel mosfet on gnd on-resistance r on_pdmp ?7.016 ? i sd = 100 ma peak output current ( 1 ) i out_pdmp 2.3 2.7 ? a r l = 1.0 ? from -25v to tx 2.3 2.8 ? a r l = 1.0 ? from -80v to tx tx damping n-channel mosfet on gnd on-resistance r on_ndmp ?7.016 ? i sd = 100 ma peak output current ( 1 ) i out_ndmp ? -2.0 -1.8 a r l = 1.0 ? from +25v to tx ? -2.3 -2.0 a r l = 1.0 ? from +80v to tx rtzsw auto bleed high-v oltage analog switch rtzsw on-resistance ( 1 ) r rtzsw ? 238 270 ? i sd = 1.0 ma rtzsw off withstand voltage ( 1 ) v rtzsw -80 ? +80 v i sw = 100 a tx output isolation di odes and bleed resistor diode forward voltage v f ?0.961.9 vi fm = 300 ma, note 1 forward continuous current i fm ? 300 ? ma note 2 peak forward pulse current i fsm ? 3.0 ? a pw = 50 ns, note 2 total capacitance of 2-diode c t ? 3.5 ? pf at 1 mhz, 1 dbm, 0v dc, note 2 tx/rx bleed resistor to gnd r b 11 15 20 k ? note 1 electrical character istics (continued) electrical specifications: v ll = +2.5v, v dd = +5.0v, v pp0,1 = +80v, v nn0,1,2 = -80v, v gp = +10v, v gn = -10v, v sub = 0v, pws = oen = ren = 1, t a = 25c, unless otherwise s pecified. parameters in bold apply over the operating temperature range of t a = t j = 0 to +85c. parameter sym. min. typ. max. unit conditions note 1: characterized only; not 100% tested in production. 2: design guidance only.
hv7321 ds20005639a-page 8 ? 2016 microchip technology inc. trsw and rxdmp switches trsw analog switch on-resistor r trsw ?1822 ? i trsw = 1.0 ma note 1 trsw off withstand voltage v trsw -80 ? +80 v i sw = 100 a, note 1 rx to gnd protection diode v f ?1.52.2vi f = 100 ma, note 1 rxdmp switch on-resistance r rxdmp ?1721 ? i sd = 1.0 ma, note 1 rx pin to gnd capacitance c rxg ? ? 7.0 pf 1 mhz, 1 dbm, 0v dc, note 2 built-in gate drive voltage linear regulators output p-channel gate drive voltage referenced to v pp0 v pf0 -5.2 -4.6 -3.8 v v gn - v pp0 < -10v output p-channel gate drive voltage referenced to v pp1 v pf1 -5.2 -4.6 -3.8 v v gn - v pp1 < -10v output n-channel gate drive voltage referenced to v nn0 v nf0 3.3 4.2 5.2 v v gp - v nn0 > 10v output n-channel gate drive voltage referenced to v nn1 v nf1 3.3 4.2 5.2 v v gp - v nn1 > 10v output n-channel gate drive voltage referenced to gnd v pos 3.2 4.2 5.2 v output p-channel gate drive voltage referenced to gnd v neg -5.2 -4.5 -3.8 v dropout voltage of (v pp0 - v gn ) v dopf0 -2.9 -2.6 -2.4 v dropout voltage of (v pp1 - v gn )v dopf1 -2.9 -2.6 -2.4 v dropout voltage of (v gp - v nn0 )v donf0 3.0 3.3 3.6 v dropout voltage of (v gp - v nn1 )v donf1 3.0 3.3 3.6 v dropout voltage of (v neg - v gn )v doneg 2.9 3.3 3.5 v dropout voltage of (v gp - v pos )v dopos -2.8 -2.6 -2.4 v logic & clock input characteristics input logic low voltage v il 0 ? 0.2 v ll v input logic high voltage v ih 0.8 v ll ?v ll v input logic low current i il -1.0 ? ? a note 1 input logic high current i ih ??1.0 a note 1 input capacitance c in ?2.03.0pf note 2 oen switching on time t oen ? 200 ? s 50% oen rise to tx ready, note 2 oen switching off time ? 20 ? ns 50% oen fall to tx all output fets on hv rails are off, note 1 thermal protection otp n & uvlo otp n output max. pull-up v oh ? ? 5.25 v otp n output low max. voltage v ol ? ? 0.1 v at 100 a ? ? 0.4 v at 4.0 ma otp n output high current i off ??15 a 25c, at 5.25v pull-up, note 1 electrical character istics (continued) electrical specifications: v ll = +2.5v, v dd = +5.0v, v pp0,1 = +80v, v nn0,1,2 = -80v, v gp = +10v, v gn = -10v, v sub = 0v, pws = oen = ren = 1, t a = 25c, unless otherwise s pecified. parameters in bold apply over the operating temperature range of t a = t j = 0 to +85c. parameter sym. min. typ. max. unit conditions note 1: characterized only; not 100% tested in production. 2: design guidance only.
? 2016 microchip technology inc. ds20005639a-page 9 hv7321 thermal shutdown trip point t trip 125 138 160 c otp n = lo when thermal shut- down occurs, note 1 thermal shutdown hysteresis t hys ?38?c v dd ok on voltage v dduvon 3.45 3.7 4.05 v note 1 v dd uvlo trip voltage v dduvoff 3.05 3.4 3.85 v ll ok on voltage v lluvon 1.59 1.7 1.81 v ll uvlo trip voltage v lluvoff 1.39 1.6 1.71 tx output hd2 & timing characteristics second harmonic distortion hd2 ? -44 -40 db v pp0 /v nn0 = 70v launched in 100 s apart, with load of 220 pf//1k (second harmonic distortion). hd2, single-cycle inverting 5.0 mhz note 1 all these tr,tf,td values, at v pp0,1 /v nn0,1 = 70v, 220 pf//1k note 1 output rise time from 0v to v pp0 t r1 ?1012 ns output fall time from 0v to v nn0 t f1 ?1012 output rise time from v nn0 to v pp0 t r2 ?1719 output fall time from v pp0 to v nn0 t f2 ?1719 output rise time from v nn0 to 0v t r3 ? 10 13.5 output fall time from v pp0 to 0v t f3 ? 10 13.5 propagation delay rise time 1 t dr1 ?1618 ns propagation delay fall time 1 t df1 ?1618 propagation delay rise time 2 t dr2 ? 17.5 19 propagation delay fall time 2 t df2 ? 17.5 19 propagation delay rise time 3 t dr3 ?1416 propagation delay fall time 3 t df3 ?1416 output rise time from 0v to v pp1 t r4 ?1517 ns all these tr,tf,td values at v pp0,1 /v nn0,1 = 70v, 220 pf//1k note 1 output fall time from 0v to v nn1 t f4 ?1517 output rise time from v nn1 to v pp1 t r5 ?2427 output fall time from v pp1 to v nn1 t f5 ?2427 output rise time from v nn1 to 0v t r6 ?1013 output fall time from v pp1 to 0v t f6 ?1013 propagation delay rise time 4 t dr4 ?1517 ns propagation delay fall time 4 t df4 ?1517 propagation delay rise time 5 t dr5 ?1618 propagation delay fall time 5 t df5 ?1618 propagation delay rise time 6 t dr6 ?1517 propagation delay fall time 6 t df6 ?1517 delay time matching with sel = l ? t d1 ?1.52.0ns p to n, ch.-to-ch. matching in ic, typ. at v pp0,1 /v nn0,1,2 = 70v , 220 pf//1k , note 1 delay time matching with sel = h ? t d2 ?1.52.0ns electrical character istics (continued) electrical specifications: v ll = +2.5v, v dd = +5.0v, v pp0,1 = +80v, v nn0,1,2 = -80v, v gp = +10v, v gn = -10v, v sub = 0v, pws = oen = ren = 1, t a = 25c, unless otherwise s pecified. parameters in bold apply over the operating temperature range of t a = t j = 0 to +85c. parameter sym. min. typ. max. unit conditions note 1: characterized only; not 100% tested in production. 2: design guidance only.
hv7321 ds20005639a-page 10 ? 2016 microchip technology inc. trsw switch on delay time t trsw 130 180 230 ns from pos = 0 & neg = 0, note 1 trsw switch off delay time 8 12 16 ns from pos = 1 or neg = 1, note 1 rtzsw switch on delay time t rtzsw 130 180 240 ns from pos = 0 & neg = 0, note 1 rtzsw switch off delay time 11 21 31 ns from pos = 1 or neg = 1, note 1 rxdmp damp switch on delay time t rxdmp 3 10 15 ns from pos = 1 or neg = 1, note 1 rxdmp damp switch off delay time 0.55 1.4 2.35 us from pos = 0 & neg = 0, note 1 pws = 0 to 1 mode change time t mc ? 220 ? ns note 2 output max. frequency range f out ? 20 ? mhz 100 ? resistor load, note 2 re-timing clock frequency f clk 10 ? 220 mhz note 2 re-timing clock rise & fall times t rc ,t fc ?0.55.0ns note 2 set-up time, pos/neg to clk t su 2.0 ? ? ns note 2 hold time, clk to pos/neg t h 1.0 ? ? ns note 2 clock time low ( 2 ) t clk_lo 2.0 ? 100 ns clk input must be activated before pos and neg inputs are high. clk input must be deacti- vated after pos and neg inputs are low. clock time high ( 2 ) t clk_hi 2.0 ? 100 clock recognition time ( 1 ) t clk_rec ?2.0? clock release time ( 1 ) t clk_rls 150 330 500 temperature characteristics unless otherwise indicated, all parameters apply with v ll = +2.5v, v dd = +5.0v, v pp0,1 = +80v, v nn0,1,2 = -80v, v gp = +10v, v gn = -10v, v sub = 0v, oen = ren = 1 parameters sym. min. typ. max. units conditions temperature ranges operating ambient temperature range t oa 0?+85c storage temperature range t st -55 ? +150 c maximum junction temperature t j ? ? +130 c total power dissipation pd ? 3.0 ? w thermal package resistances (64ld 9 mm x 9 mm vqfn) junction-to-ambient thermal resistance ? ja ?16.3? c/w jedec (2s2p) 4l pcb 114.3 mm x 76.2 mm x1.6 mm t a = 85c junction-to-board thermal resistance ? jb ? 2.55 ? c/w jedec (2s2p) 4l pcb 114.3 mm x 76.2 mm x1.6 mm t a =85c junction-to-case top thermal resistance ? jc ?0.2?c/w jedec (2s2p) 4l pcb 114.3 mm x 76.2 mm x1.6 mm t a =85c electrical character istics (continued) electrical specifications: v ll = +2.5v, v dd = +5.0v, v pp0,1 = +80v, v nn0,1,2 = -80v, v gp = +10v, v gn = -10v, v sub = 0v, pws = oen = ren = 1, t a = 25c, unless otherwise s pecified. parameters in bold apply over the operating temperature range of t a = t j = 0 to +85c. parameter sym. min. typ. max. unit conditions note 1: characterized only; not 100% tested in production. 2: design guidance only.
? 2016 microchip technology inc. ds20005639a-page 11 hv7321 table 1-1: input output logic truth table (transparent, clk = 0) function otp n logic inputs tx output rtzsw & trsw cwsw rxdmp oen mode pws clk sel neg pos pulsed-echo mode ( 1 ) 11 0 1 0 0 0 0 rtz off off on 11 0 1 0 0 0 1 v pp0 off off on 11 0 1 0 0 1 0 v nn0 off off on 11 0 1 0 0 1 1rtz+ ( 4 ) on off off 11 0 1 0 1 0 0 rtz off off on 11 0 1 0 1 0 1 v pp1 off off on 11 0 1 0 1 1 0 v nn1 off off on 1 1 0 1 0 1 1 1 high z off off on cw mode-0 ( 2 ) 11 0 0 0 0 0 0 rtz off off on 11 0 0 0 0 0 1 v pp0 off off on 11 0 0 0 0 1 0 v nn0 off off on 11 0 0 0 0 1 1rtz+ ( 4 ) on off off 11 0 0 0 1 0 0 rtz off off on 11 0 0 0 1 0 1 v pp1 off off on 11 0 0 0 1 1 0 v nn1 off off on 1 1 0 0 0 1 1 1 high z off off on cw mode-1 ( 3 ) 11 1 x x other than 011 high z off on on 011rtz+ ( 4 ) on off off device disabled x 0 x x x x x x high z off off on thermal protection activated 0 x x x x x x x high z off off on note 1: in pulsed-echo mode, low duty cycle must be used due to the ic pow er dissipation limit. 2: when pws = 0, v pp1 /v nn1 output current is reduced for low-voltage cw mode-0. v pp0 /v nn0 output current is unaffected when pws = 1, as in pulsed-echo mode. 3: in cw mode = 1, the cwsw is turned on to use external cw waveform at cw in , if the channel sel=neg=pos=0. 4: when sel = 0, neg = 1, pos = 1, the channel is in receiving mode (rtz+).
hv7321 ds20005639a-page 12 ? 2016 microchip technology inc. table 1-2: input output logic truth table (with clk re-timing, clk ? 10mhz) function otp n logic inputs tx output rtzsw & trsw cwsw rxdmp oen mode pws clk sel neg pos pulsed-echo mode ( 1 ) 11 0 1 000rtzoffoff on 11 0 1 001v pp0 off off on 11 0 1 010v nn0 off off on 11 0 1 011rtz+ ( 4 ) on off off 11 0 1 100rtzoffoff on 11 0 1 101v pp1 off off on 11 0 1 110v nn1 off off on 11 0 1 111high zoffoff on cw mode-0 ( 2 ) 11 0 0 000rtzoffoff on 11 0 0 001v pp0 off off on 11 0 0 010v nn0 off off on 11 0 0 011rtz+ ( 4 ) on off off 11 0 0 100rtzoffoff on 11 0 0 101v pp1 off off on 11 0 0 110v nn1 off off on 11 0 0 111high zoffoff on cw mode-1 ( 3 ) 11 1 xx other than 011 high z off on on 011rtz+ ( 4 ) on off off device disabled x0 x xxxxxhigh zoffoff on thermal protection activated 0x x xxxxxhigh zoffoff on note 1: in pulsed-echo mode, low duty cycle must be us ed due to the ic power dissipation limit. 2: when pws = 0, v pp1 /v nn1 output current is reduced for low-voltage cw mode-0. v pp0 /v nn0 output current is unaffected when pws = 1, as in pulsed-echo mode. 3: in cw mode = 1, the cwsw is turned on to use external cw waveform at cwin, if the channel sel=neg=pos=0. 4: when sel = 0, neg = 1, pos = 1, the channel is in receiving mode (rtz+).
? 2016 microchip technology inc. ds20005639a-page 13 hv7321 1.1 typical timing diagrams figure 1-1 shows the timing of control inputs and rtz, t/r and rxdmp switches per each channel of the hv7321. upon the completion of a receiving period, an rtz period (sel, neg, pos = 000) should be asserted before transmitting again. figure 1-1: logic input timing diagram. figure 1-2: tx output timing diagram. figure 1-3: timing diagram of hv7321 tx output and switches in cw mode-1 driven by external cw source. 001 010 000 010 001 101 110 100 110 101 t dr1 t r1 t f2 t df2 t r3 t dr3 t f1 t df1 t r2 t dr2 t f3 t df3 t dr4 t r4 t f5 t df5 t r6 t dr6 t f4 t df4 t r5 t dr5 t f6 t df6 tx output sel input neg input pos input tx output v pp0 sel input neg input pos input rtzsw switch t rtzsw(off) rx time on pws input t mc cw-mode trsw switch rxdmp switch rtz+ b-mode on off rtz tx time on off off v nn0 rtz v pp1 v nn1 rtz rtz+ 000 000 000 000 011 011 011 001 010 101 110 on on off t trsw(off) t rxdmp(on) t rtzsw(on) t trsw(on) t rxdmp(off) rx time external cw source vcw+ external cw source sel input neg input pos input mode input external cw source vcw- hv7321 tx output rtz hi-z per ch cw delay in external cw source rtz cw end mode = 0 mode = 1 000 000
hv7321 ds20005639a-page 14 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005639a-page 15 hv7321 2.0 typical performance curves figure 2-1: i llq vs. temperature. figure 2-2: i pp0q vs. temperature. figure 2-3: i pp1q vs. temperature. figure 2-4: i ddq vs. temperature. figure 2-5: i nn0q vs. temperature. figure 2-6: i nn1q vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or ta bles, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0 0.1 0.2 0.3 0.4 0.5 0 255075100 i llq ( a) temperature (c) 0 1 2 3 4 0 255075100 i pp0q ( a) temperature (c) 0 1 2 3 0 255075100 i pp1q ( a) temperature (c) 0 10 20 30 40 50 0 255075100 i ddq ( a) temperature (c) -4 -3 -2 -1 0 0255075100 i nn0q ( a) temperature (c) -4 -3 -2 -1 0 0 255075100 i nn1q ( a) temperature (c)
hv7321 ds20005639a-page 16 ? 2016 microchip technology inc. figure 2-7: tx output waveform, 1-cycle 5 mhz with 220 pf//1k load. figure 2-8: tx output hd2, 1-cycle inverting, 5 mhz with 220pf//1k load. -100 -80 -60 -40 -20 0 20 40 60 80 100 00.10.20.30.4 a b time (s) voltage (v) -60 -50 -40 -30 -20 -10 0 10 20 0 5 10 15 20 25 30 a + b a - b frequency (mhz) hd2 = -52.9 db amplitude (db)
? 2016 microchip technology inc. ds20005639a-page 17 hv7321 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . table 3-1: pin function table pin symbol description 1cw in0 external cw input for channel 0 2 sel1 sel input logic pin selects transmission high-voltage rails for channel 1. if sel = 0, select v pp0 /v nn0 . if sel = 1, select v pp1 /v nn1 . see ta b l e 1 - 1 . 3neg1 neg input logic pin turns on/off corresponding output n-channel mosfet for channel 1. see ta b l e 1 - 1 . 4pos1 pos input logic pin turns on/off corresponding output p-channel mosfet for channel 1. see table 1-1 . 5cw in1 external cw input for channel 1 6oen output enable logic input pin. when oen = v ll , the transmitter outputs are enabled. when oen = 0, the transmitter outputs are disabled. 7pws logic input pin. when pws = 0, the output fets for v pp1 and v nn1 are scaled down to reduce the output current for cw mode-0. 8 clk re-timing clock input pin. connect clk to ground for transparent mode. 9, 22, 59 gnd ground 10 v ll input logic power supply pin 11 ren enable pin for the built-in voltage regulators.see section section 4.3 ?operation modes? for details. 12 sel2 sel input logic pin selects transmission high-voltage rails for channel 2. if sel = 0, select v pp0 /v nn0 . if sel = 1, select v pp1 /v nn1 . see ta b l e 1 - 1 . 13 neg2 neg input logic pin turns on/off corresponding output n-channel mosfet for channel 2. see ta b l e 1 - 1 . 14 pos2 pos input logic pin turns on/off corresponding output p-channel mosfet for channel 2. see table 1-1 . 15 cw in2 external cw input for channel 2 16 sel3 sel input logic pin selects transmission high-voltage rails for channel 3. if sel = 0, select v pp0 /v nn0 . if sel = 1, select v pp1 /v nn1 . see ta b l e 1 - 1 . 17 neg3 neg input logic pin turns on/off corresponding output n-channel mosfet for channel 3. see ta b l e 1 - 1 . 18 pos3 pos input logic pin turns on/off corresponding output p-channel mosfet for channel 3. see table 1-1 . 19 cw in3 external cw input for channel 3 20 otp n temperature sensor open drain output 21, 60 v dd +5v supply 23 v gp +10v supply pin for the linear regulator 24, 25, 56, 57 v pp0 positive high-voltage supply pin. v pp0 must be equal to or greater than v pp1 . 26, 55 c pf0 internal linear regulator output pin. connect 2 f 10v capacitor to v pp0 . 27, 54 c nf0 internal linear regulator output pin. connect 2 f 10v capacitor to v nn0 . 28, 29, 52, 53 v nn0 negative high-voltage supply pin. v nn0 must be equal to or more negative than v nn1,2 30, 51 v nn2 negative high-voltage supply pin. v nn2 connects to the most negative supply rail. 31, 50 v nn1 negative high-voltage supply pin. v nn1 must be equal to or less negative than v nn0 . 32, 49 c nf1 internal linear regulator output pin. connect 2 f 10v capacitor to v nn1 . 33, 48 c pf1 internal linear regulator output pin. connect 2 f 10v capacitor to v pp1 . 34, 47 v pp1 positive high voltage supply v pp1 . must be equal to or lower than v pp0 . 35 tx3 channel 3 transmitter output pin
hv7321 ds20005639a-page 18 ? 2016 microchip technology inc. 36 rx3 channel 3 t/r switch output 37, 44 r gnd power ground 38 rx2 channel 2 t/r switch output 39 tx2 channel 2 transmitter output pin 40 c neg internal linear regulator output pin. connect 1 f 10v capacitor to gnd. 41 c pos internal linear regulator output pin. connect 1 f 10v capacitor to gnd. 42 tx1 channel 1 transmitter output pin 43 rx1 channel 1 t/r switch output 45 rx0 channel 0 t/r switch output 46 tx0 channel 0 transmitter output pin 58 v gn -10v supply pin for the linear regulator 61 mode cw mode selection pin. see section section 4.3 ?operation modes? . 62 sel0 sel input logic pin selects transmission high-voltage rails for channel 0. if sel = 0, select v pp0 /v nn0 . if sel = 1, select v pp1 /v nn1 . see ta b l e 1 - 1 . 63 neg0 neg input logic pin turns on/off corresponding output n-channel mosfet for channel 0. see ta b l e 1 - 1 . 64 pos0 pos input logic pin turns on/off corresponding output p-channel mosfet for channel 0. see table 1-1 . thermal pad v sub connect to ground. table 3-1: pin function table (continued) pin symbol description
? 2016 microchip technology inc. ds20005639a-page 19 hv7321 4.0 device description 4.1 overview the hv7321 is a 4-channel, 5-level ultrasound transmitter with built-in t/r switches, output protection diodes and clamp diodes. the hv7321 can provide up to ? 2.6a and the output voltage swing can be up to ? 80v. the hv7321 supports both transparent and re-timing mode. the re-timing clock frequency can support up to 220 mhz. the re-timing feature helps reduce the output jitter introduced by the driving fpga. 4.2 recommended power-up sequence powering up/down in any arbitrary sequence will not cause any damage to the device. the powering-up sequences in ta b l e 4 - 1 are only recommended in order to minimize possib le in-rush current. figure 4-1 shows the timing diagram of related signals. figure 4-1: power-on events and power-saving time diagram. 4.3 operation modes there are five modes of operation: device disabled, output disabled, pulsed-echo mode, cw mode-0 and cw mode-1. 4.3.1 device enable mode in device disabled mode, the regulators are turned off when ren is low. the regulators are on when ren = v ll . all regulators are on except v neg and v pos for power saving when ren = 1. when ren is low, oen = x (oen = 1 or 0) since device is disabled. refer to ta b l e 4 - 2 . 4.3.2 output high z mode in output disabled mode, regulators are enabled ren = 1 and oen = 0 (output enable logic input) and output pins (tx0-3) are in high z state. oen = 1 enables the outputs. 4.3.3 pulsed-echo mode pulsed-echo mode (b-mode) enables the 5-level waveform generation. oen = 1, mode = 0, and pws = 1 enable pulsed-echo mode after hv7321 powers on. sel/neg/pos inputs of desired channel determine the corresponding tx output pulse. table 4-1: power-up sequence step power-up description 1v ll on with logic signal low 2v dd , v gp and v gn on 3ren=1 4v pp0,1 and v nn0,1 on 5 oen = 1 & logic control signal active pgd internal v cpos output v ll input v dd input v dd > v dduvon v gp input v pp input oen input ren input internal v dd power-good signal |v gn | |v nn | t oen_on v cneg output v pp s v cpf v cnf s v nn (3v) ready to work (power saving) table 4-2: ren & oen logic inputs ren oen device tx output 0 x disabled high z 1 0 enabled high z 1 1 enabled on
hv7321 ds20005639a-page 20 ? 2016 microchip technology inc. 4.3.4 cw mode-0 cw mode-0 enables continuous wave mode provided solely by the hv7321. oen = 1, mode = 0 and pws = 0 activate cw mode-0. fpga selects v pp1 and v nn1 amplitudes via sel/neg/pos inputs. in theory, v pp0 and v nn0 can be selected but this is strongly discouraged since v pp0 and v nn0 usage increases power consumptio n and causes excessive heating in cw mode-0. 4.3.5 cw mode-1 cw mode-1 is enabled using an external cw signal source for continuous wave mode. oen = 1 and mode = 1 activate cw mode -1. external cw signals can connect to any of cw in0-3 . in this mode, the cw signal source also feeds the clk input. see table 4-3 for details. 4.3.5.1 external cw beamformer option (cw mode-1) the hv7321 has built-in cw switches that allow the use of an external cw beamformer to further minimize jitter and phase noise on cw waveforms. this mode is called cw mode-1. one suggested external cw beamformer is the md1730, which has very low phase noise and 8-channel cw output. a pair of hv7321s can operate with the md1730 as an 8-channel cw waveform generator. see figure 4-2 . the md1730 supports both differential and single-ended signals using clkp and clkn inputs. the md1730 enables setting the cw output phase delay and frequency for channels via spi. please refer to the md1730 data sh eet for more information. figure 4-2: hv7321 + md1730 integration. table 4-3: mode & pws logic inputs mode pws state 0 0 cw mode-0 0 1 pulsed-echo 1 x cw mode-1 table 4-3: mode & pws logic inputs mode pws state x0 1 of 4 channles +1v to +8v +2.5v rx0 -10v txrw to next hv7321 clk to other ics ctrn[3:0] otp n dt[63:0] tx fpgai/os oen ren mode pws otp n sel0 neg0 pos0 sel3 neg3 pos3 clk cw in0 cw in1 cw in2 cw in3 gnd v sub sub v gn rx1-3 tx1-3 r gnd r gnd rxdmp rx0 tx0 v nn1 v pp1 v nn0 v pp0 v gp v pp v ll +5v +10v 0v to +80v 0v to -80v 0v to -80v 0v to +80v trsw trsw rtzsw v pf1 v nf1 v pf0 v nf0 decode & level shift +2.5v +5v +10v v gp v pp v ll c pf v cw+ ckb0 v ll cbe1 clk clk v ll cbe0 vcw+ ckb1 cw0 cw1 cw2 cw3 cw4~7 to next hv7321 cw in0 3 vcw- c nf v gn dap gnd sub other cw channels 1 of 8 channels md1730 vcw- v pf v nf cw fre. dvdr & phase delay spi lvds clk cwsw hv7321 -1v to -8v -10v en spim cs sdo sdi sck clk clk cbe0,1
? 2016 microchip technology inc. ds20005639a-page 21 hv7321 4.4 high temperature protection when overtemperature is detected, otpn = 0 and all outputs are high z regardless of oen and the other logic control inputs. table 4-4 shows the relationship between ren, oen inputs, otpn output, and the corresponding device status. table 4-4: ren, oen, otp n vs. device status otp n ren oen device tx output 0 0 x disabled high z 0 1 x enabled high z 1 0 x disabled high z 1 1 0 enabled high z 1 1 1 enabled on
hv7321 ds20005639a-page 22 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005639a-page 23 hv7321 5.0 packaging information 5.1 package marking information legend: xx...xproduct code or customer-specific information yyear code (last digit of calendar year) yyyear code (last 2 digits of calendar year) wwweek code (week of january 1 is week ?01?) nnnalphanumeric traceability code pb-free jedec design ator for matte tin (sn) * this package is pb-free. the pb-f ree jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for customer-specific information. package may or may not include the corporate logo. 3 e 3 e 64-lead vqfn (9 x 9 x 1.0 mm) example hv7321k6 1642256 3 e
hv7321 ds20005639a-page 24 ? 2016 microchip technology inc. note: for the most current package drawings, see the microchip packaging specification at www.microchip.com/packaging.
? 2016 microchip technology inc. ds20000000a-page 25 hv7321 appendix a: revision history revision a (october 2016) ? original release of this document.
hv7321 ds20000000a-page 26 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20000000a-page 27 hv7321 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . part no. xx package device device: hv7321: 4-ch. 5-level 80v high-voltage ultrasound pulser with t/r switches package: k6 = very thin plastic quad flat pack, no lead package, 9.00 x9.00 x1.0 mm body, 0.50 mm pitch, 64-lead (vqfn) environmental: g = lead (pb)-free/rohs-compliant package examples: a) HV7321K6-G: 4-ch. 5-level 80v high-voltage ultrasound pulser with t/r switches 64ld 9x9 mm vqfn package -x environmental
hv7321 ds20000000a-page 28 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20000000a-page 29 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microc hip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem arks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-1033-1 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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